The logic circuits employed within modern computing equipment must be subjected to the epitome of quality assurance techniques. Within computer logic circuitry, failure rates which in other technologies would be considered outstandingly good are considered as catastrophically bad. For example, a logic circuit which drops or picks up a bit in a stream of binary data once every one million bits would be worthless. A single erroneous bit in a data stream can cause an astronomical data error. A single misplaced bit in an instruction can completely change the action taken by the computer in interpreting and executing the instruction so as to cause an irrecoverable error. Accordingly, many manufacturers of logic circuitry have gone to a bootstrap approach wherein known good and constantly monitored logic circuitry is used to check out the new circuitry for malfunctions contained therein.
The malfunctioning of a logic circuit can be very subtle. Such circuitry typically contains numerous flip-flops, gates, and the like interconnected to provide signals between one another and as inputs from and outputs to other logic circuits contained within a major piece of equipment such as a digital computer. Unlike a water valve or an automobile jack which is either working or nonworking, a logic circuit can be working except for one or more unique stimulation patterns. That is, the logic circuit may provide an erroneous output only when stimulated by a first binary input such as 101010 followed by an input of 010101. Any other combination of binary input sequences (of six bits in this case) will cause the logic circuit to behave in a normal manner. Moreover, the aforementioned problem of 101010 followed by 010101 may be an intermittent problem. That is, the malfunction does not occur every time the foregoing sequence is input to the logic circuit. A digital computer thus becomes the only practical device for exercising the logic circuit board inasmuch as the digital computer can be programmed to stimulate the logic circuit with all possible permutations and combinations of input stimulus possible, on a repetitive basis. Moreover, the computer never tires or ceases to diligently watch for malfunctions. Thus, the one in a million malfunction over an extended testing period will be caught.
To accomplish such testing, mechanical fixtures or jigs are provided wherein the printed circuit boards containing the logic circuit can be inserted in a manner substantially identical with their manner of insertion during their intended use. Provision may be made for plugging in one printed circuit board to the fixture or many, depending on the testing installation. A computer is connected to the mechanical fixture so as to be able to output to the board or boards contained therein and to input from the boards. The computer is also connected to typical peripheral devices such as an input-output (I/O) keyboard and display unit as well as magnetic tape, disc, or other mass storage device for the accumulation and storage of data and programs employed in the testing procedure.
Referring briefly to FIG. 1, a simplified drawing of a logic circuit board as tested by the present invention is shown generally as 10. Logic circuit board 10 comprises a printed circuit board 12 having an input contact 14 and an output contact 16 adapted for electrically mating with a contacting receptacle. Between input contact 14 and output contact 16, a logic circuit generally indicated as 18 is disposed comprising a plurality of interconnected logic elements labeled G1 through G11 respectively. Logic elements G1-G11 could be gates, flip-flops, or the like. Throughout the logic circuit 18 there are various "nodes" labeled A through L which are available for testing. It is to be understood that the logic circuit board 10 of FIG. 1 is shown in simplified form only and that the logic circuit boards tested by the present invention typically employ more than a single input and single output contact.
If a stimulating input signal is applied to input contact 14, the signal appearing at node A will appear as an input to both logical elements G1 and G2. As can be seen from FIG. 1, even a basically simple logic circuit has built-in complexities. Thus, the output of element G11 finally appearing at node L and the output contact 16 is a function of the logic states at nodes K and I corresponding to the status of elements G10 and G4 respectively. The state of element G10 is, of course, a function of the states of elements G8 and G9 and the state of element G4 is a function of the state of elements G2 and G3, and so forth. Thus, before the output state of element G11 stabilizes, it may fluctuate or change logic state a number of times as the inputs thereto fluctuate in response to changes in state of the preceding elements G1 through G10 taking place.
Typically, such logic circuitry is tested by applying a sequence of preselected input signals to the input contact 14 at spaced intervals sufficient to allow the last elements connected to the output contact 16 to stabilize. The output signals at the output contact 16 corresponding to the output states of the output element are compared to the known proper signal for response by the logic circuit to the particular stimulating input. This approach is useful under normal circumstances in detecting a complete malfunction within the logic circuitry 18 causing a completely erroneous output at the output contact 16. The proper output signal appearing at the output contact 16 is not a guarantee of proper operation of the logic circuit 18, however. In certain instances, one or more of the elements G1 through G11 comprising logic circuit 18 may be "stuck." Such a condition is referred to in many cases as a "stuck at zero" or "S-A-O" fault.
Input and output data associated with a simulation of a circuit such as that shown in FIG. 1 is shown in FIG. 2--both for a normal or "good" circuit and for a circuit having a S-A-O fault at node "I." Referring first to FIG. 2(a), the input is initially a logical zero (0) which, by the time 11.30, has caused the output to go from some unidentified unitialized state to a logical zero (0). At the time 0.0 (designated as T1) a logical one (1) is applied to the input causing the input to change from the previous 0 logic state to a 1 logic state. By the time 1.50, the input has stabilized as a logical 1, where it remains throughout the balance of the sequence. By contrast, it can be seen that the change of the input from a 0 to a 1 state causes a number of logic changes in the output prior to its final stabilization. At time 4.70, the change labeled C1 begins, which causes the output to change from a logical 0 to a logical 1 by time 6.20. At time 6.40, however, change C2 begins, causing the output to switch logical state back to a logical 0 by time 7.90. At time 11.30, change C3 begins, whereby the output once again goes to a logical 1 state by time 12.80. Finally, at time 12.90, the output begins its final change (labeled C4) which causes the output to reach its final stabilized logic state of 0 by time 14.40.
By contrast, now referring to FIG. 2(b), if the prior art technique of applying a change in input at time T1, delaying until time T4, and then sensing the output were applied, the proper logical 0 state would be read. As can be seen by comparison of the total output sequence, however, with node I stuck at zero the changes at C1 and C2 never occur. The logical 1 at time 6.20 (labeled T2) never occurs. Thus, even by applying one known prior art technique wherein the status of the output immediately preceding its final stabilization is sampled would not detect the stuck at zero fault of the present example. That is, by sampling at time T3 according to the aforementioned technique one would detect the logical 1 at the output followed by change C4 to the final stabilized output of 0. As can be seen, this would not result in the detection of the stuck at zero fault.
Wherefore, it is the object of the present invention to provide a method and apparatus for testing logic circuits capable of detecting such malfunctions as hereinbefore described both for a complete logic circuit assembly and for subassemblies thereof whereby complex logic faults within logic circuits can be detected and isolated to subcircuits thereof.